The semiconductor integrated circuit (IC) industry has experienced rapid growth. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC manufacturing are needed.
For example, as semiconductor devices, such as field-effect transistors (FETs), are scaled down through various technology nodes, controlling end-to-end critical dimensions and profile control of the scaled down devices is becoming more difficult. Accordingly, although existing approaches to forming stressor regions for IC devices have been generally adequate for their intended purposes, they have not been entirely satisfactory in all respects.